This invention relates to a nonvolatile semiconductor memory, more particularly to a nonvolatile semiconductor memory having uniform program and erase characteristics and capable of high-density integration.
Nonvolatile reprogrammable semiconductor memories such as an electrically erasable programmable read-only memory (EEPROM) and a flash memory are ideal for storing data that only occasionally need to be modified, because they can retain the data while power is off. Memories of this type are used in many computing devices and systems.
FIG. 1 shows a sectional view of the memory cell structure of a conventional reprogrammable nonvolatile memory. The semiconductor substrate 11 comprises crystalline silicon. A floating gate 13 disposed above the substrate 11, a control gate 15 disposed above the floating gate 13, and a source area 17 and drain area 19, which are formed by doping the substrate 11 on either side of the gates 13 and 15 with impurities, are the principal elements of a memory cell 21. These elements form a field-effect transistor with an active region comprising the source area 17, the drain area 19, and a channel 22 disposed in the substrate 11 between the source and drain areas. These elements are covered by an insulating film 23, in which a contact hole 25 is opened to permit a metal interconnecting line 27 (a bit line) to make contact with the drain area 19. The source and drain areas 17 and 19 of the memory cell 21 are shared with other memory cells adjacent in a first direction, which will be marked as the y-direction in the drawings.
FIG. 2 shows a plan view of several memory cells in a conventional nonvolatile memory, using the same reference numerals as in FIG. 1. FIG. 1 corresponds to a section through the line I--I. The y-direction is vertical in FIG. 2; the perpendicular direction (now horizontal) is denoted the x-direction. It can be seen that the source areas 17 extend in the x-direction so as to interconnect all memory cells disposed in the same horizontal row. The control gates 15 are also interconnected in the x-direction, forming word lines. The floating gates 13 (hatched) are not interconnected.
FIG. 3 is a simplified plan view from which the gates, word lines, and bit lines have been removed to show the shape of the active region 31. Due to the sharing of source and drain areas between adjacent memory cells in the y-direction, and the extensions of the source areas in the x-direction, the active region 31 has the general form of a rectilinear grid. In areas not occupied by the active region 31, the surface of the substrate is oxidized to create insulating field areas 33.
Referring again to FIG. 2, the source areas 17 are held at a constant electrical potential by means of metal source lines 35 that run parallel to the bit lines 27 in the y-direction. Each metal source line 35 makes contact with the source areas 17 in the substrate through contact holes 37 which are opened in the insulating layer 23 shown in FIG. 1. One metal source line 35 is provided for every m bit lines 27, where m is a positive integer. For example, one metal source line 35 may be provided per sixteen bit lines 27.
One problem with the conventional memory structure illustrated in FIGS. 1 to 3 is that the source resistance of a memory cell varies depending on its distance from the metal source lines 35. If there is one metal source line 35 for every sixteen bit lines 27, for example, the eighth memory cell from a metal source line 35 has a higher source resistance than a memory cell disposed adjacent to a metal source line 35.
The source resistance can become quite substantial. For example, if the x-pitch of the memory cells is 2.0 .mu.m (indicated by the capital letter X in FIG. 2), the width (in the y-direction) of the source areas 17 is 0.5 .mu.m, and the sheet resistivity of the source areas is 50 .OMEGA., then the source resistance of the eighth memory cell, disposed midway between two metal source lines, is (50.times.2.0.times.8/0.5)/2=800 .OMEGA.. The final division by two in this formula takes account of the parallel electrical paths to two metal source lines 35.
A high source resistance degrades programming and erasing characteristics, i.e. it takes longer to program and erase the memory cells. The large variation in source resistance from one cell to another furthermore makes it difficult to program and erase the cells accurately, increasing the risk of overprogramming and overerasing.
Another problem is that providing metal source lines 35 every m bit lines increases the effective x-pitch of the memory cells by a factor of (m+1)/m, which is a disadvantage from the standpoint of integration density.
Impediments to dense integration also exist in the y-direction. The y-pitch of the memory cells, indicated by the capital letter Y in FIG. 2, is the sum of five quantities: Y.sub.1 (one-half the y-dimension of the source area 17); Y.sub.2 (the gap between the gates 13 and 15 and the active region 31); Y.sub.3 (the gate length); Y.sub.4 (the gap between the gates 13 and 15 and the contact hole 25); and Y.sub.5 (one-half the y-dimension of the contact hole 25). The gap Y.sub.2 is needed to ensure that the floating gates 13 and control gates 15 cross the active regions 31 only in the channel areas of the memory cells, and do not overlap the extensions of the source areas 17 in the x-direction. The need for the gap Y.sub.4 is apparent from FIG. 1; it keeps the gates from being short-circuited to the bit lines. Both gaps Y.sub.2 and Y.sub.4 must be big enough to allow a mask overlay tolerance during the memory fabrication process; this restricts the achievable integration density.
On the basis of 0.6 -.mu.m design rules, the above quantities can be estimated as follows: Y.sub.1 =0.25 .mu.m, Y.sub.2 =0.25 .mu.m, Y.sub.3 =0.7 .mu.m, Y.sub.4 =0.3 .mu.m, and Y.sub.5 =0.3 .mu.m. The y-pitch Y is accordingly 1.8 .mu.m. Details will be omitted, but the x-pitch with the same 0.6-.mu.m design rules is 2 .mu.m.
Another problem occurring in the conventional memory is that, due to mask misregistration, in some cases the floating gates 13 may be disposed quite close to the edges of the field areas 33, where the field oxide is relatively thin, while in other cases they are disposed farther from the edges, where the field oxide is relatively thick. This leads to variation in the potential of the floating gates 13, which is a source of further nonuniformity in programming and erasing characteristics.